DESIGN OF LOW POWER ADC USING 0.18μm CMOS TECHNOLOGY
نویسنده
چکیده
The dual slope integrating analog to digital converter (ADC) is an efficient one for wireless transmission of ECG signals. Normally the dual slope ADCs are used for high resolution applications and the accuracy is very high. The main advantage of the ADC design is its high speed with low power. The dual slope ADC consists of integrator, comparator and a ten bit binary counter. To design integrator by using low power op-amp; comparator by using CMOS transistor and a binary counter by using JK flip-flop which are consume less power. These components have to be incorporated in a system with a single control switch that produces the control signals and dual ramp at the input side. Finally the digital output is occur at the terminal of binary counter. This work was done using CADENCE Virtuoso environment with 180nm technology.
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